
use crate::metadata::ir::*;
pub(crate) static REGISTERS: IR = IR {
    blocks: &[Block {
        name: "Sdmmc",
        extends: None,
        description: Some("Secure digital input/output interface"),
        items: &[
            BlockItem {
                name: "power",
                description: Some("power control register"),
                array: None,
                byte_offset: 0x0,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Power"),
                }),
            },
            BlockItem {
                name: "clkcr",
                description: Some("SDI clock control register"),
                array: None,
                byte_offset: 0x4,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Clkcr"),
                }),
            },
            BlockItem {
                name: "argr",
                description: Some("argument register"),
                array: None,
                byte_offset: 0x8,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Argr"),
                }),
            },
            BlockItem {
                name: "cmdr",
                description: Some("command register"),
                array: None,
                byte_offset: 0xc,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cmdr"),
                }),
            },
            BlockItem {
                name: "respcmdr",
                description: Some("command response register"),
                array: None,
                byte_offset: 0x10,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Respcmdr"),
                }),
            },
            BlockItem {
                name: "respr",
                description: Some("response 1..4 register"),
                array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
                byte_offset: 0x14,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("RespxR"),
                }),
            },
            BlockItem {
                name: "dtimer",
                description: Some("data timer register"),
                array: None,
                byte_offset: 0x24,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Dtimer"),
                }),
            },
            BlockItem {
                name: "dlenr",
                description: Some("data length register"),
                array: None,
                byte_offset: 0x28,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Dlenr"),
                }),
            },
            BlockItem {
                name: "dctrl",
                description: Some("data control register"),
                array: None,
                byte_offset: 0x2c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Dctrl"),
                }),
            },
            BlockItem {
                name: "dcntr",
                description: Some("data counter register"),
                array: None,
                byte_offset: 0x30,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Dcntr"),
                }),
            },
            BlockItem {
                name: "star",
                description: Some("status register"),
                array: None,
                byte_offset: 0x34,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Star"),
                }),
            },
            BlockItem {
                name: "icr",
                description: Some("interrupt clear register"),
                array: None,
                byte_offset: 0x38,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Icr"),
                }),
            },
            BlockItem {
                name: "maskr",
                description: Some("mask register"),
                array: None,
                byte_offset: 0x3c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Maskr"),
                }),
            },
            BlockItem {
                name: "fifocnt",
                description: Some("FIFO counter register"),
                array: None,
                byte_offset: 0x48,
                inner: BlockItemInner::Register(Register {
                    access: Access::Read,
                    bit_size: 32,
                    fieldset: Some("Fifocnt"),
                }),
            },
            BlockItem {
                name: "fifor",
                description: Some("data FIFO register"),
                array: None,
                byte_offset: 0x80,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Fifor"),
                }),
            },
        ],
    }],
    fieldsets: &[
        FieldSet {
            name: "Argr",
            extends: None,
            description: Some("argument register"),
            bit_size: 32,
            fields: &[Field {
                name: "cmdarg",
                description: Some("Command argument"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 32,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Clkcr",
            extends: None,
            description: Some("SDI clock control register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "clkdiv",
                    description: Some("Clock divide factor"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 8,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "clken",
                    description: Some("Clock enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pwrsav",
                    description: Some("Power saving configuration bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "bypass",
                    description: Some("Clock divider bypass enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "widbus",
                    description: Some("Wide bus mode enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 2,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "negedge",
                    description: Some("SDIO_CK dephasing selection bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "hwfc_en",
                    description: Some("HW Flow Control enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cmdr",
            extends: None,
            description: Some("command register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "cmdindex",
                    description: Some("Command index"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 6,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "waitresp",
                    description: Some("Wait for response bits"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 2,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "waitint",
                    description: Some("CPSM waits for interrupt request"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "waitpend",
                    description: Some("CPSM Waits for ends of data transfer (CmdPend internal signal)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cpsmen",
                    description: Some("Command path state machine (CPSM) Enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sdiosuspend",
                    description: Some("SD I/O suspend command"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Dcntr",
            extends: None,
            description: Some("data counter register"),
            bit_size: 32,
            fields: &[Field {
                name: "datacount",
                description: Some("Data count value"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 25,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Dctrl",
            extends: None,
            description: Some("data control register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dten",
                    description: Some("DTEN"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dtdir",
                    description: Some("Data transfer direction selection"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dtmode",
                    description: Some("Data transfer mode selection 1: Stream or SDIO multibyte data transfer"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dmaen",
                    description: Some("DMA enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dblocksize",
                    description: Some("Data block size"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 4,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rwstart",
                    description: Some("Read wait start"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rwstop",
                    description: Some("Read wait stop"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rwmod",
                    description: Some("Read wait mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sdioen",
                    description: Some("SD I/O enable functions"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Dlenr",
            extends: None,
            description: Some("data length register"),
            bit_size: 32,
            fields: &[Field {
                name: "datalength",
                description: Some("Data length value"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 25,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Dtimer",
            extends: None,
            description: Some("data timer register"),
            bit_size: 32,
            fields: &[Field {
                name: "datatime",
                description: Some("Data timeout period"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 32,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Fifocnt",
            extends: None,
            description: Some("FIFO counter register"),
            bit_size: 32,
            fields: &[Field {
                name: "fifocount",
                description: Some("Remaining number of words to be written to or read from the FIFO"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 24,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Fifor",
            extends: None,
            description: Some("data FIFO register"),
            bit_size: 32,
            fields: &[Field {
                name: "fifodata",
                description: Some("Receive and transmit FIFO data"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 32,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Icr",
            extends: None,
            description: Some("interrupt clear register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "ccrcfailc",
                    description: Some("CCRCFAIL flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dcrcfailc",
                    description: Some("DCRCFAIL flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ctimeoutc",
                    description: Some("CTIMEOUT flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dtimeoutc",
                    description: Some("DTIMEOUT flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txunderrc",
                    description: Some("TXUNDERR flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxoverrc",
                    description: Some("RXOVERR flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdrendc",
                    description: Some("CMDREND flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdsentc",
                    description: Some("CMDSENT flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dataendc",
                    description: Some("DATAEND flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "stbiterrc",
                    description: Some("STBITERR flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dbckendc",
                    description: Some("DBCKEND flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sdioitc",
                    description: Some("SDIOIT flag clear bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Maskr",
            extends: None,
            description: Some("mask register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "ccrcfailie",
                    description: Some("Command CRC fail interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dcrcfailie",
                    description: Some("Data CRC fail interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ctimeoutie",
                    description: Some("Command timeout interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dtimeoutie",
                    description: Some("Data timeout interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txunderrie",
                    description: Some("Tx FIFO underrun error interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxoverrie",
                    description: Some("Rx FIFO overrun error interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdrendie",
                    description: Some("Command response received interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdsentie",
                    description: Some("Command sent interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dataendie",
                    description: Some("Data end interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "stbiterre",
                    description: Some("STBITERR interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dbckendie",
                    description: Some("Data block end interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdactie",
                    description: Some("Command acting interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txactie",
                    description: Some("Data transmit acting interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxactie",
                    description: Some("Data receive acting interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txfifoheie",
                    description: Some("Tx FIFO half empty interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxfifohfie",
                    description: Some("Rx FIFO half full interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txfifofie",
                    description: Some("Tx FIFO full interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxfifofie",
                    description: Some("Rx FIFO full interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txfifoeie",
                    description: Some("Tx FIFO empty interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxfifoeie",
                    description: Some("Rx FIFO empty interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txdavlie",
                    description: Some("Data available in Tx FIFO interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxdavlie",
                    description: Some("Data available in Rx FIFO interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sdioitie",
                    description: Some("SDIO mode interrupt received interrupt enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Power",
            extends: None,
            description: Some("power control register"),
            bit_size: 32,
            fields: &[Field {
                name: "pwrctrl",
                description: Some("PWRCTRL"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 2,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Respcmdr",
            extends: None,
            description: Some("command response register"),
            bit_size: 32,
            fields: &[Field {
                name: "respcmd",
                description: Some("Response command index"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 6,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "RespxR",
            extends: None,
            description: Some("response 1..4 register"),
            bit_size: 32,
            fields: &[Field {
                name: "cardstatus",
                description: Some("see Table 132"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 32,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Star",
            extends: None,
            description: Some("status register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "ccrcfail",
                    description: Some("Command response received (CRC check failed)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dcrcfail",
                    description: Some("Data block sent/received (CRC check failed)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "ctimeout",
                    description: Some("Command response timeout"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dtimeout",
                    description: Some("Data timeout"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txunderr",
                    description: Some("Transmit FIFO underrun error"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxoverr",
                    description: Some("Received FIFO overrun error"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdrend",
                    description: Some("Command response received (CRC check passed)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdsent",
                    description: Some("Command sent (no response required)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dataend",
                    description: Some("Data end (data counter, SDIDCOUNT, is zero)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "stbiterr",
                    description: Some("Start bit not detected on all data signals in wide bus mode"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dbckend",
                    description: Some("Data block sent/received (CRC check passed)"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "cmdact",
                    description: Some("Command transfer in progress"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txact",
                    description: Some("Data transmit in progress"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxact",
                    description: Some("Data receive in progress"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txfifohe",
                    description: Some("Transmit FIFO half empty: at least 8 words can be written into the FIFO"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxfifohf",
                    description: Some("Receive FIFO half full: there are at least 8 words in the FIFO"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txfifof",
                    description: Some("Transmit FIFO full"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxfifof",
                    description: Some("Receive FIFO full"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txfifoe",
                    description: Some("Transmit FIFO empty"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxfifoe",
                    description: Some("Receive FIFO empty"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "txdavl",
                    description: Some("Data available in transmit FIFO"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rxdavl",
                    description: Some("Data available in receive FIFO"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sdioit",
                    description: Some("SDIO interrupt received"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
    ],
    enums: &[],
};
